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Dr. S. RAVI CHAND


Qualification B.Tech, M.Tech, Ph.D
Institution Joining Date 28-01-2021
E-mail Id hod.ece@nnrg.edu.in
Teaching Experience 21 Years
Area of Specialization VLSI and Embedded Systems
Research Publications

S. Ravi Chand, B. Kalivaraprasad, LVS Narayana, S. Sree Hari Raju, K. Rama Lakshmi, “Security and Privacy concerns of Mobile Cloud Computing”, The ICSVCE-2022: International Conference on Advances in Signal Processing, VLSI, Communications and Embedded Systems held at Vardhaman College of Engineering, Hyderabad, on 29th & 30th July , 2022

A Pramod Kumar, B. KV Prasad, A. Jayalakshmi, and S. Ravi Chand, a paper titled , “A Novel Voltage Level-Up Shifter Design for Power Efficient Methods Using Dual Current Mirror Technique”, in the Proceedings of 3rd International Conference on Machine Learning, Advances in Computing, Renewable Energy and Communication MARC 2022

Manthandi Periannasamy S, S, Ravi Chand S and Gopalakrishnan S “Analysis of Artificial Intelligence Enabled Intelligent Sixth Generation (6G) Wireless Communication Networks”, IEEE International Conference on Data Science and Information System (ICDSIS-2022) in association with IEEE Bangalore Section, IEEE Information Theory Society, and IEEE Computer Society Bangalore Chapter during 29-30 July 2022 at Malnad College of Engineering, Hassan, Karnataka.

N.C.Sendhil Kumar, A Srinivas, N.Selva ganesh, S.Ravi Chand, “An Empirical Model for the Investigation of Effective Intrusion Detection Systems by Using K-Nearest Neighbor (KNN) and Fuzzy (Fuzzy KNN) Algorithms in Mobile Ad-Hoc Network (MANET)" Turkish Online Journal of Qualitative Inquiry (TOJQI)Volume 12, Issue 10, October2021: 1569-1578.

Rajasekhar Turaka, S. Ravi Chand, Tavanam Venkata Rao, Kumara Swamy.V, “FPGA Implementation of Radix-2 Pipelined FFT Algorithm for High Throughput Applications”, Ravi chand Sankuru in the Third International Conference on Advances in Electrical and Computer Technologies 2021 (ICAECT 2021) held at Hotel Aloft, Coimbatore, Tamil Nadu, India during 29 - 30, October 2021

S. Ravi chand, Rajasekhar Turaka, C.V. Krishna Reddy, “Study on the Implementation of FPGA for Efficient Vedic Multiplier” in AICTE Sponsored 5th National Conference on Knowledge Based Inventive Electronics & Telecommunication Systems held between 25 – 27 August 2021 at KKR & KSR Institute of Technology and Sciences, Guntur. ISBN: 978- 81-951436-2-7, page no.52-54.

Rajasekhar Turaka, S. Ravi chand, C.V. Krishna Reddy, “Data Security using Cryptography and Steganography Techniques” in AICTE Sponsored 5th National Conference on Knowledge Based Inventive Electronics & Telecommunication Systems held between 25 – 27 August 2021 at KKR & KSR Institute of Technology and Sciences, Guntur ISBN: 978-81-951436-2-7, page no.52-54.

S.Ravichand, S.Balaji K.Naresh R.Shanmukharao, “RTL Design Quality Checks for Soft IPs”, published in Journal of Engineering Science (J E S), ISSN:0377- 9254, Volume 11, Issue 2 Feb-„20, UGC approved group 'II' multidisciplinary journal.

S.Ravichand, S.Balaji K.Naresh, P.Krishna, “Register Transfer Logic Design Quality Checks for Soft Intellectual Property”, published in International Journal of Research and Analytical Reviews –IJRAR, , E-ISSN 2348-1269, P- ISSN 2349-5138, a Scopus journal, Volume 7, Issue 1, pg.364-369, Feb 2020

S.Ravi chand, M. Sasamka Devika, G. Akhila, “Enhanced Safety System Vessels by Using Arduino” published in International Journal of Innovative Science, Engineering & Technology-IJISET, Vol. 7 Issue 2, February 2020 ISSN (Online) 2348 – 7968 | Impact Factor (2019)

Md.Tanveer Ahamad, I Srikanth, P Kumar Raj, S.Ravichand “Implementation OfHospital Alerting System And Virtual Driving Using Arduino” in © 2019 IJRAR February 2019, Volume 6, Issue 1,E-ISSN 2348-1269, P- ISSN 2349-5138.

S.Ravi chand, Dr.M.Sailaja, Dr.T.Madhu, „Fault Tolerant Multicore Architecture with Hardware Reconfigurable Unit‟ published in SYLWAN JOURNAL Poland, Vol. 161, Issue. 8, 2017 ISSN: 0039-7660, impact factor :0.263 2018

S.Ravi Chand K. R Rao Presented a paper titled, “A Modernistic Approach to Design Fault Tolerant Circuit Using LFSR with Low Power Dissipation” in International Conference on Emerging Trends in Engineering, Management, Science andTechnologies (ICEEMST-2018) on 03 / 03 / 2018 Sai Prakasam Group of Institutions, Ongole.

S.Ravi chand, Dr.M.Sailaja, Dr.T.Madhu, “SRAM based Fault Tolerant Technique for Detection of Transient Errors in Processors through Pass Transistor Logic” published in International Journal of Computer Applications (IJCA) USA, October 2017 , IJCA, Volume 176 – No.3- ISSN: 0975 – 8887

S.Ravi chand, Dr. M.Sailaja, Dr.T.Madhu, „Design and Analysis of Transient Fault Tolerance in SRAM with different NT Techniques‟ IJCA, USA, October 2016,Volume 151 – No.3, ISSN: 0975 – 8887

S.Ravi chand, K.V.Ganesh, M.Sailaja „On-Chip Generation of Accumulator Based 3- Weighted Test Pattern Generation for Synchronous VLSI Circuits‟ IJAER, Indexed ,Vol. 10 No.1 2015, ISSN 0973-4562, page 700-704 online ISSN 1087-1090.

S.Ravi Chand K. Rudra Rao Published a paper titled, “A Modernistic Approach to Design Fault Tolerant Circuit Using LP-LFSR with Low Power Dissipation” International Journal of Electronics and Communication Engineering ISSN: 2348 – 8549 - Special Issue- March 2017

S.Ravi chand, Dr.M.Sailaja, Dr.T.Madhu, “Fault Diagnosis For Using Tpg Low Power Dissipation And High Fault Coverage”, IEEE Conference Publications Pages: 1 - 5, DOI: 10.1109/ICCIC.2010.5705884, 978-1-4244-5967-4/10/$26.00 ©2010 IEEE

S.Ravi Chand K. Rudra Rao Presented a paper titled, “A Modernistic Approach to Design Fault Tolerant Circuit Using LP-LFSR with Low Power Dissipation” in International Conference on Emerging Trends in Engineering, Management, Science and Technologies (ICEEMST-2017) on 03 / 03 / 2017 RISE Krishna Sai Prakasam Group of Institutions, Ongole.

S.Ravi chand, Dr.M Sailaja, Dr.T.Madhu, “A BIST Scheme for Low Energy Testing Using a Multiple Single Input Change Vector (SICV) in a Test Pattern Generation” IJSRM, Volume -04, Issue – 2 , 2016, ISSN (e): 23281-3418

S. Ravichand, T. Madhu, M. Sailaja “A Self-Repairing Digital System with High- Quality Scalability and Fault Coverage” International Journal of Emerging Research in Management &Technology ISSN: 2278-9359 (Volume-6, Issue-8)

G.Lashmi Prasanna, S.Ravi Chand and Dr.T.Madhu published paper “Implementation of RISC based 2D-DWT architecture for image compression” in IJETCSE volume-23 Issue-5 September 2016

S.Ravichand, K.V.Ganesh, M.Sailaja “on chip generation of accumulator based 3- weightead test pattern generation for synchronous VLSI circuits” presented in “IEEE sponsored 9th International conference on Intelligent Systems & Control (ISCO) 2015, on 10-11th Jan 2015 at Karpagam Engineering College, Tamilnadu.

S.Ravichand, T.Gopal Krishna, “A novel BIST scheme for low energy testing using a multiple single input charge vector (SICV) in a test pattern generation” in International conference in Eng tech ICAET-2015 on 28-03-2015 at Jaya Eng college-Chennai.

S.Ravichand, S.Durga Babu, A.Chaitanya, “Fault tolerant circuit using LP-LFSR with low power dissipation analysis in ICACI-2015 on 05-04-2015 at Jawahar Engineering College, Saligramam, Chennai.

Vadapalli Srinivas, S.Ravichand, T.Gopal Krishna presented a paper entitled “A BIST scheme for low energy testing using multiple single input change vector (MSICV)” in a TPG published in IJETCSE vol-13 issue 4- March 2015 ISSN:0976-1353 page 60-63. 28.

S.Ravi chand, V.Srinivas, Dr.M Sailaja, Dr.T.Madhu, “A BIST Design For Self Testable And Cost Efficient Single Port Ram Based FFT Processor”, Proceedings of the Multi Conference 2011: 2nd (ICSSA 2011) & 1st International Conference on Intelligent Systems & Data Processing (ICISD 2011). Universal-Publishers Boca Raton, Florida USA 2011 ISBN: 978-1-6123-3002-0

V.Srinivas, S.Ravi chand, Dr. Ch. Santhi Rani Dr.T.Madhu, “Model Based Speech Enhancement And Coding”, in IJTET, International Journal of Applied Engineering Research 1087-1090 Volume 6, Number 18 (2011) Special Issues pp. 2568-2572

S.Ravichand, M.Sailaja, G.Bharathi, presented a paper titled “Design of a low power 8 bit ALU” on 21 to 13 April 2010 held at Dayanand Sagar institutions, Bangalore.

V.Srinivasarao, Dr P.Rajesh Kumar, G.V.H.Prasad, S.Ravichand ― Discrete Cosine Transform Vs Discrete Wavelet Transform: An Objective Comparison of Image Compression Techniques for JPEG Encoder ‖Published in International Journal of Advanced Engineering and application, Jan 2010

M.V.Ganeswar Rao, S.Ravichand, T.Madhu, P.Ravikumar, presented a paper on “Design of Low Power Processor Embedded core using VHDL” in the National conference on 11th and 2th February 2007 held at St Joseph engineering college, Ketty, Tamilnadu.

FDP and Workshops

One week FDP on "Amazon Web Services” " from 22nd August 2022 to 27th August 2022 organized by Dr D Y Patil Institute of Management & Research, Akurdi – Pune in collaboration with Brinovision Solutions Pvt Ltd and AICTE.

Completed Innovation Ambassador Training Series Foundation level and Advanced level courses through Institution’s Innovation Council in 2021-22.

One week AICTE Training And Learning (ATAL) Academy Online FDP on "Latest Technological Developments For System On Chip (SoC) Applications" from 2021-7-26 to 2021-7-30 at GIET University.

One week ATAL FDP on "Design Thinking to nurture Creativity and Innovation leading to Entrepreneurship” " from 14-06-2021 to 18-06-2021 organized Dr D Y Patil Institute of Management & Research, Akurdi – Pune.

One week International FDP on "Challenges in Energy Management for Smart Cities" Organized by Department of Electrical and Electronics Engineering in association with Centre for Renewable Energy Technology-AVIT from 07-06-2021 to 11-06-2021.

One week short term course on “VLSI Signal Processing” organized by IIT Kharagpur, between 21st to 29th December 2006.

One week training program on “Instructional design and Delivery” at Sri Vishnu Engineering For women, Bhimavaram by NITTTR Madras in 2006.

One week training program on “Counseling and career Guidance” at Sri Vishnu Engineering For women, Bhimavaram by NITTTR Madras 2007.

Two Week AICTE-MHRD Sponsored short term course on Analog IC design at NIT Calicut in June 2010.

Two week program on “Research Methodologies” organized by JNTUK Kakinada in may 2012.

Two week program on “Intellectual Property Rights and patents” organized by JNTUK Kakinada in May 2012.

Patents

Indian Patent, “Design and Implementation for Traffic Violation Detection of Vehicles using OCR Algorithm Based on Artificial Intelligence Technique”, Publication Date : 17/09/2021Application No.202141040652 A

Granted Australian Patent with title “Machine Learning Technique to Analyze the Condition of Covid-19 Patients based on their saturation Levels” Patent number: 2021105808 on 6 October 2021 Commissioner of Patents, Australia.

Indian Patent, “Cloud Based Smart System for Urban Buildings”, Publication Date:15/07/2022Application No. No.202241039020 A

Memberships
  • Member of IEEE.
  • Life Member of ISTE.
  • Member of IAENG (Singapore).